1. Field of the Invention
This invention generally relates to the manufacture of semiconductor devices, and more particularly to a process of forming self-aligned contact structures in a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits generally include many conductive layers and active areas separated from one another via an insulating dielectric material. To electrically connect conductive layers and/or active areas separated by one dielectric layer, a contact hole or opening is formed through the dielectric layer and filled with a conductive material in physical contact with the conductive layers. Conventionally, the formation of the contact hole involves a number of technical processes, principally photolithography, etching and deposition processes.
As the size of semiconductor devices continuously decreases, the formation of the contact structure is subject to a narrower misalignment margin. Improper alignment of the contact structure may affect and even cause failure of the electrical connection within the semiconductor device. As a result, more stringent requirements are imposed on the manufacturing processes implemented to form the contact structure.
To overcome the problem of contact misalignment, one method commonly implemented uses the topography of the electrical device to ensure proper electrical connection of the contact hole. This method can advantageously form self-aligned contacts.
U.S. Pat. No. 6,329,292 issued to Hung et al., the disclosure of which is incorporated herein by reference, proposes a process of forming self-aligned contacts in a memory device. The memory device includes adjacent gate electrodes formed on a silicon substrate. Spacers made of silicon nitride are formed on the sidewalls of the gate electrodes, which then are covered with a dielectric layer. To establish electrical connection with an actively doped area of the substrate between two gate electrodes, an etching process is conducted through the dielectric layer to expose the underlying substrate. The etching process includes two etching steps implemented with different etching chemistries to ensure that the contact hole is formed without damaging adjacent structures. In particular, the second etching chemistry has to be correctly dosed to prevent undesirable polymer formation which might affect dielectric layer etching.
U.S. Pat. No. 6,613,683 issued to Hwangbo et al., the disclosure of which is also incorporated herein by reference, proposes another method of forming a self-aligned contact in a semiconductor device. The idea of the proposed method is to monitor the presence of a chemical compound produced while etching the dielectric layer. A predetermined level reached by the chemical compound indicates that the etching has reached the shoulders of the spacers. To prevent the spacer from over-etching, a second etching process with a modified etching chemistry is performed until the substrate is exposed, thereby forming the contact hole.
Practically, the foregoing methods do not bring satisfactory results in forming the contact hole. In particular, the spacers might still be eroded along with the etching of the dielectric layer and the bottom liner layer to expose the substrate. The thinner spacers adversely reduce the breakdown voltage window of the semiconductor device, and consequently its performance.
These technical issues call for an improved manufacturing method of the semiconductor devices to more efficiently and effectively form a contact structure without damaging the spacers.